ADZS-BF533-EZLITE【PDF 14/64 页】KIT W/BOARD EVAL FOR ADSP-BF533

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ADSP-BF531 / ADSP-BF532 / ADSP-BF533

As shown in Figure 9 , the core clock (CCLK) and system

Table 7. Core Clock Ratios

peripheral clock (SCLK) are derived from the input clock

(CLKIN) signal. An on-chip PLL is capable of multiplying the

CLKIN signal by a user programmable 0.5 ? to 64 ? multiplica-

Signal Name

Divider Ratio

Example Frequency Ratios

(MHz)

tion factor (bounded by specified minimum and maximum

VCO frequencies). The default multiplier is 10 ? , but it can be

modified by a software instruction sequence. On-the-fly

frequency changes can be effected by simply writing to the

PLL_DIV register.

CSEL1–0

00

01

10

11

VCO/CCLK VCO CCLK

1:1 300 300

2:1 300 150

4:1 400 100

8:1 200 25

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

BOOTING MODES

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have

two mechanisms (listed in Table 8 ) for automatically loading

÷ 1, 2, 4, 8

CCLK

internal L1 instruction memory after a reset. A third mode is

CLKIN

PLL

0.5 to 64

VCO

÷ 1 to 15

SCLK

provided to execute from external memory, bypassing the boot

sequence.

Table 8. Booting Modes

SCLK

SCLK

CCLK

133 MHz

BMODE1 –0 Description

00 Execute from 16-bit external memory (bypass

Figure 9. Frequency Modification Methods

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Table 6. Example System Clock Ratios

Example Frequency Ratios

boot ROM)

01 Boot from 8-bit or 16-bit FLASH

10 Boot from serial master connected to SPI

11 Boot from serial slave EEPROM/flash (8-,16-, or 24-

bit address range, or Atmel AT45DB041,

AT45DB081, or AT45DB161serial flash)

The BMODE pins of the reset configuration register, sampled

during power-on resets and software-initiated resets, imple-

ment the following modes:

? Execute from 16-bit external memory – Execution starts

Divider Ratio

Signal Name

SSEL3–0

0001

0101

1010

(MHz)

VCO/SCLK VCO SCLK

1:1 100 100

5:1 400 80

10:1 500 50

from address 0x2000 0000 with 16-bit packing. The boot

ROM is bypassed in this mode. All configuration settings

are set for the slowest device possible (3-cycle hold time;

15-cycle R/W access times; 4-cycle setup).

? Boot from 8-bit or 16-bit external flash memory – The flash

boot routine located in boot ROM memory space is set up

The maximum frequency of the system clock is f SCLK . The divi-

sor ratio must be chosen to limit the system clock frequency to

its maximum of f SCLK . The SSEL value can be changed dynami-

cally without any PLL lock latencies by writing the appropriate

values to the PLL divisor register (PLL_DIV). When the SSEL

value is changed, it affects all of the peripherals that derive their

clock signals from the SCLK signal.

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7 . This programmable core clock capability is useful for

fast core frequency modifications.

using asynchronous Memory Bank 0. All configuration set-

tings are set for the slowest device possible (3-cycle hold

time; 15-cycle R/W access times; 4-cycle setup).

? Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit

addressable, or Atmel AT45DB041, AT45DB081, or

AT45DB161) – The SPI uses the PF2 output pin to select a

single SPI EEPROM/flash device, submits a read command

and successive address bytes (0x00) until a valid 8-, 16-, or

24-bit addressable EEPROM/flash device is detected, and

begins clocking data into the processor at the beginning of

L1 instruction memory.

? Boot from SPI serial master – The Blackfin processor oper-

ates in SPI slave mode and is configured to receive the bytes

of the LDR file from an SPI host (master) agent. To hold off

the host device from transmitting while the boot ROM is

busy, the Blackfin processor asserts a GPIO pin, called host

wait (HWAIT), to signal the host device not to send any

Rev. I

|

Page 14 of 64 |

August 2013

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